Analog Manager Agent
The Analog Manager Agent coordinates analog circuit design in Cadence Virtuoso, including schematic creation, layout, simulation, and DRC/LVS checks.
The manager owns design decisions, acceptance criteria, and recovery when a stage fails. It delegates execution to the Virtuoso sub-agent, one stage at a time, and can directly inspect existing cellviews, technology information, and simulation results.
Prerequisites
- A Linux host with NEX installed and your NEX license and LLM provider configured.
- Cadence Virtuoso with a valid tool license and access to the project's PDK and design libraries.
- Cadence Spectre and the appropriate device models for simulation stages.
- Siemens Calibre and the appropriate DRC/LVS rule decks for signoff stages.
The Virtuoso integration runs batch tools in the configured project environment. Project setup records library paths, environment setup, tool executables, models, and rule decks in virtuoso_project.json.
Usage
Start an Analog Manager session from your working directory:
Describe the circuit or existing project, the target technology, and your design requirements. Include supply voltage, load, temperature, process corners, and performance targets where relevant.
For example:
Inspect the existing analog project in ./amplifier. Read the amplifier schematic
and available simulation results, then identify which gain, bandwidth, and power
targets still need verification before proposing changes.
For a new project, provide the PDK and library locations and ask the manager to set up the project before editing any cellviews.
Workflow and Delegation
The manager selects the next stage based on the design and available evidence:
- Setup: Create or open the project and inspect its technology and libraries.
- Schematic: Create or edit the circuit and testbench, or import a CDL/SPICE netlist, then verify the schematic.
- Simulation: Export the netlist, run Spectre, and measure the circuit against its targets.
- Layout: Place devices, route connections, and inspect the resulting geometry.
- Signoff: Run the configured Calibre DRC and LVS checks.
- Reports: Inspect existing cellviews and results without making changes.
Stages run sequentially. The Virtuoso sub-agent returns evidence for its assigned stage; the manager evaluates the result and decides whether to advance or delegate a correction. A failed tool run, DRC violation, or incorrect LVS result is reported as incomplete work.
Importing a Netlist
To create schematics from an existing CDL/SPICE netlist, provide the source file, target library and cell, and any known device mappings. The manager delegates the import to the Virtuoso schematic stage, which uses Spice In and checks the result by re-exporting it.
Import ./netlists/amplifier.cdl into the amplifier cell in my analog_work library.
Verify the imported schematic by re-exporting it and report any differences.
Ask me about unmapped devices or existing cells before choosing mappings or overwriting them.
Unmapped devices, libraries missing from cds.lib, and overwriting existing cells require your decision. See Virtuoso Netlist Import and Export for the expected inputs and results.
Results and Limits
Layout edits invalidate earlier LVS results, including edits made to fix DRC violations. The manager must obtain fresh DRC results and, when a schematic exists, a correct LVS result for the edited cell before reporting the layout complete. Lost connections or stale LVS results remain blockers until resolved and checked again.
The analog agents are instructed to preserve PDK, technology-library, and foundry files, including rule decks, device models, and layer maps. If a change is needed, they report the issue and work on project copies.
Performance figures should include the process corner, temperature, supply, and load at which they were measured. The manager distinguishes measured results from derived values and assumptions.
The current toolset does not perform parasitic extraction. Simulation results are pre-layout; extraction and post-layout simulation remain separate work before post-layout performance can be established.
If Virtuoso has a cellview open in a GUI, reopen it after batch edits to see the changes. A cellview lock or unavailable EDA license can block execution; NEX reports the blocker and any required user action.