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Virtuoso Sub-Agent

The Virtuoso Sub-Agent executes a single stage of analog circuit work using the Cadence Virtuoso toolset and returns a structured report to the Analog Manager.

Delegation-only

Start the manager with nex --agent=analog. The manager delegates Virtuoso work when needed; nex --agent=virtuoso is not a valid top-level CLI mode.

Supported Stages

Stage Scope
setup Create or open the project and inspect its technology. No cellview edits.
schematic Create or edit schematics and testbenches, import CDL/SPICE netlists, inspect symbols, and export netlists. No layout edits, simulation, or signoff.
layout Create or edit layouts, stream GDS, and compare layouts. No schematic edits or signoff.
simulation Export netlists, run Spectre, and measure results. No cellview edits.
signoff Run Calibre DRC and LVS and report their results. No cellview edits.
reports Inspect existing cellviews and results. Read-only.

The sub-agent receives the project facts and acceptance criteria for one stage. It reports and stops after that stage; design decisions and recovery remain with the manager. For example, a simulation that exposes a testbench error requires a new schematic-stage delegation to correct it.

Project and Tool Requirements

The integration requires Linux and the installed, licensed EDA tools needed for the selected stage. See the Analog Manager prerequisites.

An existing project is identified by its directory containing virtuoso_project.json. The manager passes that directory when known; initial setup can create the project configuration. A supplied project path that does not exist is rejected before the sub-agent starts.

Virtuoso operations on one project run sequentially. Concurrent operations can block on the project lock and return a busy result.

Netlist Import and Export

The schematic stage can use import_netlist to create schematics from a CDL/SPICE netlist through Cadence Spice In. Supply the netlist path, target library and cell, and any known device mappings. The import is checked by re-exporting the result; the report includes any round-trip differences.

If device models cannot be mapped, a required library is missing from cds.lib, or target cells already exist, the agent asks for your decision before proceeding. It does not guess device mappings or choose to overwrite existing cells.

Netlist exports use export_netlist. For CDL export, provide the team's cdl_template or cdl_include_file project settings when required. If an export fails or differs from the expected GUI export, the agent reports the error and required inputs instead of hand-writing or patching the netlist.

Returned Report

The report includes:

  • A summary and a task_status of success, partial, or failed.
  • Actions taken, findings, and cellviews inspected or modified.
  • Paths of artifacts created or modified.
  • Verification evidence and schematic, layout, simulation, DRC, and LVS status where applicable.
  • Blockers and recommended next actions when acceptance criteria are not met.

Success requires evidence that the stage met its acceptance criteria. DRC violations or an incorrect LVS result are reported as partial work, and a stage that could not run is reported as failed.

Layout edits can report lost_connections and mark earlier LVS results as lvs_stale, including results for affected parent cells. These findings must be resolved and signoff rerun before the layout can be reported complete. A prior LVS pass does not establish correctness after an edit.

The agent is instructed to leave PDK, technology-library, and foundry files unchanged, and use project copies when changes are needed.

Simulation results are pre-layout: the current toolset does not perform parasitic extraction or establish post-layout performance.